dsPIC33CH support

dsPIC33CH family is the first Microchip dual core 16 bits MCU. Architecture and peripherals are similar to dsPIC33CK, the simple core version.

A lot of peripherals (UART, Timer...) are not compatible with others dsPIC ranges.

This family have variations of flash memory, pin count and CAN FD for 5XX subfamily.

Secondary core is marked with final S1. Secondary core does not have same peripherals. They have 4 - 31 kb of ram and 24 - 134 kb of PRAM.

Main features

Common devices

Devices list

65 devices on August 2023, plus relative secondary core with a final S1 which are similar core.

MP3XX vs MP4XX -> CPU with VDD core from internal BUCK converter (MP4XX lose 4 IOs). MP6XX vs MP7XX -> CPU with VDD core from internal BUCK converter (MP7XX lose 4 IOs).

MP3XX vs MP6XX -> 2 CAN Fd. MP4XX vs MP7XX -> 2 CAN Fd.

MP20X subfamily

Base device.

MP30X subfamily

MP20X with more peripherals and memory :

• Primary core :

• 1 more SPI
• 1 more QEI

• Secondary core :

• 1 more UART
• 1 more SPI
• 1 more QEI

MP40X subfamily

MP30X with VDD core from internal BUCK converter (MP4XX lose 4 IOs).

MP50X subfamily

Contains all functionnalities of 20X plus CAN FD device (2 CAN Fd buses for 256k and 512k flash version).

MP60X subfamily

MP50X with more peripherals and memory :

• Primary core :

• 1 more SPI
• 1 more QEI

• Secondary core :

• 1 more UART
• 1 more SPI
• 1 more QEI

MP70X subfamily

MP60X with VDD core from internal BUCK converter (MP7XX lose 4 IOs).

Dual core usage

dsPIC33CH is the first range of dsPIC with two cores in one package. Each core have their own periphericals set. They share access to pins by using MUX. GPIO are shared, they can both read pins but only one can write to it. The owner of each pin is defined by the configuration word.

Memory program are also independent but the secondary program is stocked in the single flash at a special address. This space is copied to secondary's PRAM at startup. So, only one hex file is needed to program both cores.

Debug could be individual by defined debug pairs for each cores.

MCLR pin reset both cores, but a special reset could be defined for secondary only.

Clock sources are the same but they have independent PLLs and divisers.

They can comunicate by a shared memory zone with hardware arbitration, by two unidirectionnal FIFO and also by virtual pins between them. VPins are usefull for synchronisations signals.

New set of peripherals

sysclock

A new PLL block appears in this line. Each core have one, but share the same clock sources.

UART

Fully reviewed UART peripherals. Bits have quite similar name but not always in the same register. In addition to UxMODE and UxSTAT, we can found UxMODEH and UxSTATH. This new version adds also integrated hardware protocols handler.

Clock generation can be done from 4 differents sources of clock with a MUX and BRG have now a fractional mode.

Timer and SCCP

A surprising thing at the first view of global features of dsPIC33CH is the only one present timer. This one is quite similar to old ones. SCCP replace it.

SCCP peripherals are multi-functions. They can be one 32bits timer, two 16bits timers, an input capture, PWM or output capture.

CAN Fd

CAN Fd module is completely different of ECAN from dsPIC33E.

PWM

PWM modules are more precises and offers more functionalities. A complete driver write needs to be done.

IOs

A new interupt on change system are available, but still compatible with old drivers.